Hardverska linija fronta — SFR zona, IRQ i Arhitektura prekida

Uvod i teorija 

1. Računar vs. Računarski sistem (Diskusija autora i Gemini AI)

  • Koncept: Kroz analizu i dijalog koji vodim sa Gemini AI, došli smo do jasne definicije koja često buni početnike: računar u svom najčistijem obliku čine samo procesor i memorija, bez obzira na organizaciju. Međutim, sam računar ne može mnogo bez periferija. Čak je i najobičniji digitron zapravo računarski sistem, jer pored procesora i memorije ima tastaturu i displej.
  • Most ka PC-ju: Kada procesoru i memoriji dodate magistralu i periferne uređaje (senzore, serijske portove, ili kod PC-ja miša, tastaturu i grafičku kartu), dobijate računarski sistem. Intel 8051 je System-on-Chip (SoC) koji na istoj silicijumskih pločici ima integrisane ove interne "čipove" (tajmere, serijsku komunikaciju), dok sve ostalo (spoljni RAM, ADC konvertori, senzori robota) dolazi spolja.

2. Zašto nam treba IRQ? Borba za magistralu i sprečavanje "đubreta"

  • Koncept: Kada imate mnogo uređaja, svi se oni grabe za resurse sistema (memoriju i magistralu). Iz teksta o mikrosekvenceru znamo da uređaji ne smeju da postavljaju podatke na magistralu kada se njima prohte.
  • Inženjerska logika: Ako serijski kontroler primi bajt sa spoljne veze, on ne može samoinicijativno da ga gurne na magistralu podataka dok procesor npr. upisuje nešto drugo u RAM. Došlo bi do kolizije i na magistrali bismo dobili čisto đubre. Zato je uveden IRQ (Interrupt Request) — zahtev procesoru da privremeno prekine trenutni tok programa i prebaci se na prekidnu rutinu (ISR) koja će bezbedno prebaciti taj bajt iz hardverskog bafera u RAM.

3. Gde živi SFR i kako upravlja tajmerom?

  • Koncept: SFR (Special Function Registers) zona se nalazi u internoj memoriji procesora (80H - FFH). Ono što je genijalno kod 8051 jeste da se ključni registri za prekide nalaze u bit-adresibilnoj zoni. Svaki registar čija se adresa završava na 0 ili 8 (kao TCON na 88H ili IE na A8H) omogućava procesoru da direktno pristupi svakom bitu pojedinačno.
  • Kako to radi silicijum:

Kada se desi neki hardverski događaj (npr. tajmer premota brojač), sam hardver automatski upisuje logičku 1 u tačno određen bit u SFR zoni (za Tajmer 0 to je TF0, odnosno bit TCON.5). Pošto je zona bit-adresibilna, mikrosekvener na kraju instrukcije munjevito, u jednom koraku, proverava status ovog bita. Ako je TF0 == 1, procesor privremeno maskira prekide nižeg prioriteta, čuva trenutno stanje na steku i skače na prekidnu adresu 000BH gde se nalazi kod naše prekidne rutine.

4. Mit o hardverskom multithreading-u

  • Koncept: Mnogi programeri imaju glavobolje oko ovoga na početku. Ali istina je jasna: multithreading je softver, a ne hardver! [1] Procesor je u osnovi glupa sprava koja ne zna ništa o nitovima ili arhitekturi Context Switch-a.
Most ka PC-ju: Broj jezgara na modernim x86 procesorima su prosto skalirani resursi. Dva jezgra na silicijumu teoretski dupliraju brzinu i olakšavaju paralelizaciju, ali princip rada sa nitima je softverski algoritam. Pošto Intel 8051 ima procesorsko jezgro i genijalan sistem banki registara u RAM memoriji, on je savršen i 100% legitiman poligon za implementaciju mikro-threading algoritma koji ćemo demonstrirati u sledećem tekstu.

Praktični deo

U ovoj epizodi fokusirali smo se isključivo na koncept IRQ-a i vezu sa mikrosekvencerom. U sledećoj epizodi prelazimo na praksu – pogledajte kako u asembleru implementiramo multithreading sistem upotrebom timerskog IRQ-a i banke registara. Kasnije ćemo ovde povezati link.

📦 Članak i prateći materijali licencirani su pod Creative Commons CC BY 4.0 licencom uz navođenje izvora zilsel-invent.com, dok je izvorni kod pod MIT licencom.

Autor: Vladimir Savić / AI Gemini

Reference:




Location: Belgrade, Serbia

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